• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Provided is a control circuit which can discharge a charge stored in an X capacitor with certainty even when an alternating current input voltage largely fluctuates. The control circuit 11 for controlling a discharge of an X capacitor C100 connected between power source lines AC1 and AC2 having different polarities of an alternating current of an AC-DC convertor 51 which receives inputting of the alternating current, converts the alternating current into a direct current, and outputs the direct current wherein the control circuit 51 detects a change state of a voltage of the X capacitor C100, and controls the discharge such that a charge stored in the X capacitor C100 is discharged based on the change state.
    公开号:NL2026428A
    申请号:NL2026428
    申请日:2020-09-08
    公开日:2021-04-13
    发明作者:Ono Hideyuki；Hisada Shigeru
    申请人:Shindengen Electric Mfg；
    IPC主号:
    专利说明:

    [0001] [0001] The present invention relates to a control circuit which controls a discharge of a capacitor connected between power source lines having different polarities of an alternating current (AC) of an AC-DC convertor which receives inputting of the alternating current, converts the alternating current into a direct current (DC), and outputs the direct curre77nt, and a power source device provided with the control circuit.
    [0002] [0002] In the AC-DC convertor which receives inputting of an alternating current (AC), converts the alternating current into a direct current (DC), and outputs the direct current DC, in general, a capacitor (so-called X capacitor) is connected between power source lines having different polarities of an alternating current input side for preventing the generation of noises. Although noises generated by inputting of an alternating current is eliminated by the X capacitor, when the input supply of an alternating current is interrupted as in the case where a plug which supplies an alternating current to the AC-DC convertor is pulled out from an outlet, a charge stored in the above-mentioned X capacitor before the input supply of an alternating current is interrupted remains in the X capacitor. Accordingly, for ensuring safety, it is necessary to discharge a residual charge.
    [0003] [0003] As a method of discharging a residual charge stored in the X capacitor, for example, there has been known an invention disclosed in JP 2016-158310 A.
    [0004] [0004] As shown in Fig. 14, the conventional discharge circuit 940 includes: a voltage dividing circuit 941 which is formed of resistances R903 and R904 connected in series between a high voltage input starting terminal HV and a ground point; a peak hold circuit 942 which holds a peak value of a voltage divided by the voltage dividing circuit 941; a voltage comparison circuit 943 which compares a potential (voltage) Vn902 of a connection node N902 between the resistances R903 and R904 and a voltage which is obtained by proportionally reducing a voltage held by the peak hold circuit 942; a timer circuit 944 which counts a time during which the potential (voltage)
    [0005] [0005] The above-mentioned voltage comparison circuit 943 compares a value which is 30% of a peak value of the potential Vn902 of the connection node N902 and the potential Vn902 of the connection node N902, and detects whether or not the potential Vn902 becomes lower than the value which is 30% of the peak value of the potential Vn902 of the connection node N902. The timer circuit 944 counts a time during which the potential Vn902 is not lower than a voltage Vp, and when it is determined that a count time exceeds 30 ms, for example, the timer circuit 944 outputs a signal for turning on the switch S900 and the discharge switch Sd900. The timer circuit 944 is formed such that counting of the time is reset each time the potential Vn902 becomes lower than the voltage Vp, and starts counting of 30 ms.
    [0006] [0006] Fig. 15 shows operation timing of the discharge circuit 940 shown in Fig. 14. In (A) of Fig. 15, a solid line indicates a waveform of a voltage VHV of the high voltage input starting terminal HV, and a broken line indicates a value which is 30% of the peak value. In Fig. 15, (B) indicates pulses CP900 outputted form the voltage comparison circuit 943, and (C) indicates an output TMR900 of the timer circuit 944.
    [0007] [0007] As shown in Fig. 15, during a normal period T901, the pulse CP900 is outputted at a cycle corresponding to a cycle of the waveform of the voltage VHV of the high voltage input starting terminal HV. When a plug is pulled out at a timing t902, the pulse CP900 is not outputted from the voltage comparison circuit 943. Then, at a point of time 1903 which comes after a lapse of 30 ms from a point of time t901 at which a last pulse is outputted, an output TMR900 of the timer circuit 944 is changed to a high level (H level). Accordingly, the discharge switch Sd900 is turned on and hence, the X capacitor (not shown in the drawing, the X capacitor being connected to an alternating current AC power source) is discharged whereby the voltage VHV of the high voltage input starting terminal HV readily falls.
    [0008] [0008]
    [9009] [9009] Patent document 1: JP 2016-158310 A
    [0010] [0010] The prior art disclosed in the above-mentioned JP 2016-158310 A is excellent with respect to the point that a residual charge of the X capacitor is discharged. However, inventors of the present invention have found the following. In the above-mentioned prior art, for example, when a fluctuation of an alternating current AC input voltage is small as in the case of an alternating current AC100V system of a single phase inputting, a residual charge of the X capacitor can be discharged. However, when the fluctuation of the alternating current AC input voltage is large (for example, in the case of a worldwide input voltage), it is difficult to discharge a residual charge of the X capacitor with certainty.
    [0011] [0011]
    [0012] [0012] Accordingly, it is an object of the present invention to provide a control circuit and a power source device (hereinafter, “control circuit and power source device” also being referred to as “control circuit and the like”) which can discharge a charge stored in the X capacitor with certainty even when an alternating current input voltage largely fluctuates. Solution to Problem
    [0013] [0013]
    [1] [1] A control circuit according to the present invention is a control circuit for controlling a discharge of a capacitor connected between power source lines having different polarities of an alternating current of an AC-DC convertor which receives inputting of the alternating current, converts the alternating current into a direct current, and outputs the direct current, wherein the control circuit detects a change state of a voltage of the capacitor, and controls the discharge such that a charge stored in the capacitor is discharged based on the change state.
    [0014] [0014] In the above configuration, “alternating current (AC)” means a voltage or a current where directions and a positive and a negative change at a short time interval. As an example of an alternating current power source, a generally-used commercially available power source is named.
    [0015] [0015]
    [2] [2] In the control circuit according to the present invention, it is preferable that the control circuit perform detection of the change state of the voltage of the capacitor by setting a first voltage obtained by level-shifting the voltage of the capacitor and a second voltage which is increased or decreased from the first voltage, and by performing a comparison operation between a voltage obtained by sample-holding the first or the second voltage every fixed time and the first or the second voltage to which sample-holding is not applied.
    [0016] [0016] In the above configuration, "by level-shifting" a voltage means that a magnitude (or a potential) of an inputted voltage is changed and a changed voltage is outputted. For example, a voltage level of an input voltage of 100 V is lowered to a voltage of several V and the voltage is outputted. With such level-shifting, a comparison operation and the like can be easily performed.
    [0017] [0017]
    [3] [3] In the control circuit according to the present invention, it is preferable that the comparison {5 operation performed by the control circuit be a comparison operation which compares and detects a magnitude relationship of the voltage obtained by sample-holding and the voltage to which sample-holding is not applied or a comparison operation which outputs a voltage difference.
    [0018] [0018] In the above configuration, "a comparison operation which outputs a voltage difference" means, for example, a comparison operation which generates an output which corresponds to a difference between the voltages to be compared.
    [0019] [0019]
    [4] [4] In the control circuit according to the present invention, it is preferable that the control circuit perform detection of the change state of the voltage of the capacitor by detecting, assuming voltage values of the first voltage, the second voltage, and a voltage obtained by sample-holding one of the first or the second voltage as a first voltage characteristic line, a second voltage characteristic line and a sample hold voltage characteristic line which are expressed with a lapse of time respectively, an intersection between the sample hold voltage characteristic line and the voltage characteristic line of the voltage to which sample-holding is not applied out of the first and the second voltages.
    [0020] [0020]
    [0021] [0021]
    [5] [5] In the control circuit according to the present invention, it is preferable that the control circuit perform the detection of the change state of the voltage of the capacitor by comparing an output obtained by performing a comparison operation between a voltage obtained by sample-holding a first voltage obtained by level-shifting the voltage of the capacitor and the first voltage to which sample-holding is not applied with a reference voltage.
    [0022] [0022]
    [6] [6] In the control circuit according to the present invention, it is preferable that the control circuit, when a state that there is no change in the change state continues for a fixed period is detected, control the discharge such that a charge stored in the capacitor is discharged.
    [0023] [0023] In the above configuration, "a state that there is no change in the change state continues for a fixed period" means that a state where a voltage of the capacitor is substantially stable and does not change continues for a fixed period.
    [0024] [0024]
    [7] [7] In the control circuit according to the present invention, it is preferable that the control circuit perform detection that a state that there is no change in the change state continues for a fixed period by counting a time of the state that there is no change in the change state.
    [0025] [0025] Counting of a time of a state that there is no change in the change state of the voltage of the capacitor is performed such that, for example, counting of a time is started, for example, using a point of time that the change state of the voltage of the capacitor changes as a reference, and when a next change is detected, the counting of the time is reset and is again started. When the time reaches "fixed time (period)" before the next change is detected, "a state that there is no change in the change state continues for a fixed period" is brought about.
    [0026] [0026]
    [8] [8] In the control circuit according to the present invention, it is preferable that the control circuit detect a change state of at least one of rising or falling of the voltage of the capacitor, and control the discharge such that a charge stored in the capacitor is discharged based on the change state.
    [0027] [0027]
    [9] [9] In the control circuit according to the present invention, it is preferable that the control circuit detect the change state of rising of the voltage of the capacitor, and contro} the discharge such that a charge stored in the capacitor is discharged based on the change state,
    [0028] [0028]
    [10] [10] In the control circuit according to the present invention, it is preferable that the control circuit include: a first voltage generating unit which generates the first voltage obtained by level-shifting the voltage of the capacitor connected between the power source lines having different polarities; a second voltage generating unit which generates a second voltage smaller than the first voltage; a sample hold unit for sample-holding the first or the second voltage, the sample hold unit having: a sample hold capacitor for the first or the second voltage; and a sample hold switch disposed between the first or the second voltage generating unit and the sample hold capacitor; a comparison operation unit which detects the change state by performing a comparison operation between a sample hold voltage obtained by sample-holding by the sample hold unit out of the first and the second voltages and the voltage to which sample-holding is not applied out of the first and the second voltages; and a discharge unit which discharges a charge stored in the capacitor connected between the power source lines having different polarities based on the detected change state.
    [0029] [0029]
    [11] [11] In the control circuit according to the present invention, it is preferable that the control circuit include: a first voltage generating unit which generates the first voltage obtained by level-shifting the voltage of the capacitor connected between the power source lines having different polarities; a sample hold unit for the first voltage, the sample hold unit having: a sample hold capacitor for the first voltage; and a sample hold switch disposed between the first voltage generating unit and the sample hold capacitor; a comparison operation unit which detects the change state by comparing an output calculated based on a sample hold voltage for the first voltage obtained by sample-holding the first voltage by the sample hold unit and the first voltage to which sample-holding is not applied by the sample hold unit with a reference voltage; and a discharge unit which discharges a charge stored in the capacitor connected between the power source lines having different polarities based on the detected change state.
    [0030] [0030]
    [12] [12] A power source device according to the present invention includes: an AC-DC convertor which receives inputting of an alternating current and outputs a direct current; a capacitor connected between power source lines having different polarities of the alternating current; and any one of the control circuits described above which controls a discharge of the capacitor. Advantageous Effects of Invention
    [0031] [0031] According to the present invention, the control circuit detects the change state of the voltage of the capacitor (X capacitor), and controls the discharge such that a charge stored in the capacitor is discharged based on the change state. Accordingly, even when an input voltage largely fluctuates, a charge stored in the capacitor can be discharged with certainty.BRIEF DESCRIPTION OF THE DRAWINGS
    [0032] [0032]
    [0033] [0033] Hereinafter, a control circuit and the like of the present invention are described based on embodiments shown in drawings. The respective drawings are schematic views, and do not always strictly reflect actual circuits, timing charts and the like. The circuits, the timing charts and the like of the respective embodiments are illustrated for an exemplifying purpose, and the present invention is not limited by these circuits and the like.
    [0034] [0034] [Embodiment 1] (1) Summary First, a power source device 101 (and a control circuit 11 of the power source device 101) according to an embodiment 1 are described with reference to Fig. 1 to Fig. 3.
    [0035] [0035] As shown in Fig. 1, the power source device 101 includes: a capacitor (X capacitor) C100 which is connected between input terminals AC1, AC2 of an alternating current AC (alternating current input power source) (between power source lines having different polarities); an AC-DC convertor 51 which converts an alternating current AC into a direct current DC and outputs a direct current output OUT to output terminals QUT, OUT2; and the like.
    [0036] [0036] The rectifier circuit REC which is formed of four diodes D21, D22, D23 and D24 is inserted between the AC input terminals ACI, AC2 (between the power source lines having different polarities), and full-wave rectification of an inputted AC is performed. A cathode of the diode D21 and an anode of the diode D23 are connected to the input terminal AC1 of an alternating current AC, and a cathode of the diode D22 and an anode of the diode D24 are connected to the input terminal AC2. A cathode of the diode D23 and a cathode of the diode D24 are connected with each other, and are connected to one side of the capacitor C21 and one input terminal of the DC-DC convertor COV. An anode of the diode D21 and an anode of the diode D22 are connected with each other, are connected to the other side of the capacitor C21 and the other input terminal of the DC-DC convertor COV, and are grounded. The capacitor C21 is a smoothing capacitor.
    [0038] [0038] Respective units of the circuit are described hereinafter.
    [0039] [0039]
    [0040] [0040] The switch SWI is a switch for sampling a voltage (voltage VA) at the connecting portion between the resistances R1 and R2, and the capacitor C1 is a capacitor for holding the sampled voltage VA. The switch SWI is turned on or off in synchronism with periodical clock pulses CP. When the clock pulse CP becomes an H level so that the switch SW1 is turned on, the switch SWI is brought into a closed state and becomes conductive. When the clock pulse CP becomes an L level so that the switch SW is tarned off, the switch SW1 is brought into an open state and becomes non-conductive. When the switch SW1 is turned on, the voltage (voltage VA) at the connecting portion between the resistances R1 and R2 is sampled. When the switch SW1 is turned off, the switch SW1 becomes non-conductive and the sampled voltage VA is held by the capacitor Cl. [It is preferable that at least a plurality of clock pulses CP exist in half period of the voltage VA.
    [0041] [0041] The connecting portion between the resistances R2 and R3 is connected to a non-inverted input terminal (+) of the comparator OPI. One side of the capacitor C1 is connected to the inverted input terminal {-) for enabling inputting of an output of the sample hold circuit SHI.
    [0042] [0042] The counting unit CNT receives inputting of the voltage VD} outputted from the comparator OP1, and counts a time using a point of time that the voltage VDI changes as a reference, and a voltage VE becomes an H level when a fixed time is counted. That is, the voltage VE outputted from the counting unit CNT, when a change of inputting of an alternating current AC (a change of the voltage VA) is not present for a fixed time or more, becomes an H level from an L level so that a discharge command is outputted so as to turn on the discharge switch SD (making the discharge switch SD conductive) and hence, a charge stored in the X capacitor C100 is discharged. The discharge switch SD is a switch disposed between the cathodes of the diodes D1 and D2 and a ground, and one side of the discharge switch SD is connected to the cathodes of the diodes DI and D2 via a discharge resistance R20, and the other side of the discharge switch SD is grounded. In a normal state where the supply of an alternating current AC is not interrupted, the voltage VE is at an L level so that the switch SD is in an open state (a non-connection state). When the supply of the alternating current AC is interrupted, and such a state is detected, the voltage VE becomes an H level so that the discharge switch SD is turned on (becoming conductive). Accordingly, a charge stored in the X capacitor C100 is discharged to a ground side via the resistance R20 (for discharging) and the switch SD.
    [0043] [0043] Fig. 2 is a view for describing operation timing of the power source device 101 (and the control circuit 11 of the power source device 101) according to the embodiment 1.
    [0044] [0044] Clock pulses CP are shown at a second stage from the top in Fig. 2. The clock pulses CP are pulses which become a basis of control timing of the entire control circuit 11. The clock pulses CP are signals which periodically take a state where a voltage is high (H level) and a state where the voltage is low (L level). In the embodiment 1, the clock pulses CP are used for timing of sample-holding performed by the sample hold circuit SH. It is preferable that a plurality of clock pulses exist within a rising period or a falling period (a half cycle) of one crest-shaped waveform (one cycle T) of the voltage VA (first voltage). The clock pulses CP can be also used as counter pulses of the counting unit (using the clock pulses CP as pulses for counting).
    [0045] [0045]
    [0046] [0046] A timing chart of the voltage VD1 outputted from the comparator OP1 is shown at a fourth stage from the top in Fig. 2. The voltage VD1 outputted from the comparator OP! is inverted each time the magnitude relationship between the voltage VBI (the voltage obtained by sample-holding the voltage VA) and the voltage VC at the connecting portion between the resistances R2 and R3 (the voltage smaller than the voltage VA) is reversed. The voltage VDI outputted from the comparator OP1 is outputted as a plurality of pulses during rising of the voltage VA (the portion on the left side of the crest-shaped waveform). On the other hand, during falling of the voltage VA (the portion on the right side of the crest-shaped waveform), a pulse-shaped voltage VDI is not outputted.
    [0047] [0047] The voltage VDI outputted from the comparator OP1 is inputted to the counting unit CNT. The counting unit CNT resets counting when the counting unit CNT detects falling of the voltage VDI from an H level to an L level, and starts counting (point of time t11). A predetermined time T11 is set in advance in the counting unit CNT. When the counting unit CNT starts counting of time from the point of time t11 and no change occurs in the voltage VDI before the time reaches the predetermined time T11, the voltage VE at a point of time t13 which comes after a lapse of the predetermined time T11 from the point of time t11 is shifted from the L level to the H level so that the discharge switch SD is turned on. Accordingly, a charge stored in the X capacitor C100 is discharged via the diode D1 (D2), the resistance R20 and the switch SD.
    [0048] [0048] Fig. 3 is a view for describing a portion shown in Fig. 2 in an enlarged manner.
    [0050] [0050] In the embodiment 1, when the input supply of an alternating current AC is normal without interruption, whether or not inputting of the alternating current AC is interrupted is detected by making use of an intersection between the voltage characteristic line of the voltage VC and the sample hold voltage characteristic line of the voltage VB1 obtained by sample-holding the voltage VA during rising of the voltage VA.
    [0051] [0051] The comparator OP1 performs a comparison operation of a magnitude relationship between the voltage VC and the sample hold voltage VBI. When the input supply of the alternating current AC is normal without interruption, the voltage VC characteristic line and the sample hold voltage VB1 characteristic line intersect with each other. In this case, the voltage VDI is inverted each time the voltage VC characteristic line and the sample hold voltage VBI characteristic line intersect with each other. Such a mode is shown in Fig. 3 in an enlarged manner.
    [0052] [0052] During a period where the voltage VA is rising, when the voltage VC is larger than the sample hold voltage VBI, the voltage VDI outputted from the comparator OP1 becomes an H level. When the voltage VC characteristic line and the sample hold voltage VB1 characteristic line intersect with each other, and the voltage VC becomes smaller than the sample hold voltage VBI, the voltage VDI outputted from the comparator OP! is inverted from the H level to an L Level. When the voltage VC characteristic line and the sample hold voltage VB1 characteristic line intersect with each other again, and the voltage VC becomes larger than the sample hold voltage VBI, the voltage VD1 outputted from the comparator OP1 is inverted from the L level to the H level.
    [0053] [0053]
    [0054] [0054] Comparison with prior art In the prior art described using Fig. 14 and Fig. 15, when the voltage VHV is set low, pulses CP900 are not generated depending on a load condition or a circuit condition so that there is a possibility that an erroneous detection occurs. This is because, for example, when a load is light and a capacitance of a filter capacitor inputted to an input part is large, with respect to a waveform of the voltage VN902 at a portion of the connection node N902, a pulsation voltage of an alternating current AC or a voltage of a valley portion of the pulsation current cannot be lowered and becomes high.
    [0055] [0055] On the other hand, in the embodiment 1, a discharge is controlled such that a change state of rising of the voltage of the X capacitor C100 is detected, and a charge stored in the X capacitor C100 is discharged based on the change state. Accordingly, a risk that an operator gets an electric shock, which is generated when a voltage VHV obtained by proportionally reducing a peak hold voltage is high, due to a residual charge of the X capacitor is low.
    [0056] [0056] In the prior art, it is necessary to peak-hold an alternating current AC voltage peak value for reflecting the alternating current AC voltage peak value to a VHV threshold value. In this case, a capacitor having a large capacitance is necessary in general. Accordingly, in integrating a control circuit, there exist several drawbacks including the following drawbacks.
    [0057] [0057] On the other hand, in the embodiment 1, it is sufficient to sample-hold a voltage which is obtained by shifting a voltage of the X capacitor C100 connected between the power source lines having different polarities of the alternating current AC power source. Accordingly, in general, IO as the sample hold capacitor, a capacitor having a small capacity compared to the prior art (peak hold capacitor) can be used. Accordingly, the control circuit can be integrated in a form that the sample hold capacitor is incorporated. Further it is unnecessary to provide a terminal for an external capacitor (peak hold capacitor) to an integrated semiconductor chip. Accordingly, it is possible to further reduce a size of the control circuit and a size of the power source device.
    [0058] [0058] [Embodiment 2] The embodiment 1 is an embodiment where a change state of rising of a voltage of the X capacitor C100 is detected. On the other hand, an embodiment 2 is an embodiment where a change state of falling of a voltage of an X capacitor C100 is detected.
    [0059] [0059] Hereinafter, the embodiment 2 is described in detail.
    [0060] [0060] Fig. 5 is a view for describing operation timing of the power source device 102 (and the control circuit 12 of the power source device 102) according to the embodiment 2.
    [0061] [0061] In a third stage from the top in Fig. 5, voltage characteristic lines which express the voltage VA, the voltage VB2 (the voltage obtained by sample-holding the voltage VC) and the voltage VC with a lapse of time are shown in a superposed manner. At a lower portion of Fig. 5, a portion L.2 of the voltage characteristic lines is enlarged, and is shown as "L2 enlarged" portion.
    [0062] [0062] A timing chart of a voltage VD2 outputted from the comparator OP2 is shown at a fourth stage from the top in Fig. 5.
    [0063] [0063] A timing chart of a voltage VE outputted from a counting unit CNT is shown at a fifth stage from the top in Fig. 5.
    [0064] [0064] In this manner, in the embodiment 2, a change state of falling of the voltage of the X capacitor C100 is detected, and a discharge is controlled such that a change stored in the X capacitor C100 is discharged based on the change state.
    [0065] [0065] [Embodiment 3] The embodiment 1 is an embodiment where a change state of rising of a voltage of the X capacitor C100 is detected, and the embodiment 2 is an embodiment where a change state of falling of the voltage of the X capacitor C100 is detected. On the other hand, an embodiment 3 is an embodiment where change states of both rising and falling of a voltage of an X capacitor C100 are detected. A circuit of the embodiment 3 is a circuit formed by combining the circuit of the embodiment 1 and the circuit of the embodiment 2, and the circuit of the embodiment 3 acquires the manner of operation and advantageous effects substantially equal to the combination of the manner of operation and advantageous effects of the embodiment 1 and the manner of operation and advantageous effects of the embodiment 2.
    [0066] [0066] Hereinafter, the embodiment 3 is described in detail. Fig. 6 is a view for describing the circuit configuration of a power source device 103 (and a control circuit 13 of the power source device 103) according to the embodiment 3. Fig. 7 is a view for describing operation timing of the power source device 103 (and the control circuit 13 of the power source device 103) according to the embodiment 3. As shown in Fig. 6, the control circuit 13 and the like according to the embodiment 3 include: the sample hold circuit SH! and the comparator OP! according to the embodiment 1 (see
    [0067] [0067] By adopting the circuit configuration shown in Fig. 6, when a voltage VA is rising, as indicated by "detection of change state of rising” in Fig. 7, voltages VA, VBI and VC depict waveforms substantially equal to the corresponding waveforms in the embodiment 1, and a voltage VD1 substantially equal to the corresponding voltage in the embodiment 1 is outputted from the comparator OP1.
    [0068] [0068] The voltage VD3 outputted from the logical sum element OR! is a voltage as the logical sum of the voltage VDI and the voltage VD2 (VD1+VD2) (see Fig. 6). Accordingly, either one of the voltage VDI outputted from the comparator OP1 and the voltage VD2 outputted from the comparator OP2 becomes an H level, the voltage VD3 becomes an H level. That is, as shown in "detection of change state of rising and falling” in Fig. 7, the voltage VD3 becomes a voltage as a logical sum of voltages outputted from both of the voltage VD1 shown in "detection of change state of rising” and the voltage VD2 shown in "detection of change state of falling”. In this specification, "logical sam” is a logical operation where a voltage of an H level is outputted when either one of inputs is at an H level, and a voltage of L level is outputted when both inputs are at an L level.
    [0069] [0069] With such an operation, a change state of the voltage can be detected by the detection of a change state of at least one of rising and falling of the voltage of the X capacitor C100 and hence, the interruption of inputting of an alternating current AC can be detected with more certainty.
    [0070] [0070] [Embodiment 4] An embodiment 4 is an embodiment where change states in both rising and falling of a voltage of an X capacitor C100 are detected in the same manner as the embodiment 3. However, the embodiment 4 is an embodiment where the change states of both rising and falling of the voltage are detected by using the same circuit as much as possible.
    [0071] [0071] Hereinafter, the embodiment 4 is described in detail.
    [0073] [0073] In this manner, when the change state of rising of the voltage of the X capacitor C100 is detected, the switches SW1, SW42 and SW43 take the above-mentioned states. This circuit has substantially the same circuit configuration as the circuit when the change state of rising of the voltage of the X capacitor C100 is detected in the embodiment 1 (or embodiment 3) shown in Fig. 1 (or Fig. 6) (the circuit formed of the sample hold circuit SH1, the comparator OP1 and the like), and acquires substantially the same manner of operation and advantageous effects.
    [0074] [0074] Detection of change state of falling of voltage of X capacitor C100 In detecting a change state of falling of a voltage of the X capacitor C100, the connection of the switches SW41, SW42 and SW43 is brought into a connection state opposite to the connection state shown in Fig. 8.
    [0075] [0075] In this manner, in detecting a change state of falling of a voltage of the X capacitor C100, the connection of the switches SW41, SW42 and SW43 takes a connection state opposite to the connection state shown in Fig. 8 described above. This circuit has substantially the same circuit configuration as the circuit when the change state of falling of the voltage of the X capacitor C100 is detected in the embodiment 2 (or embodiment 3) shown in Fig. 4 (or Fig. 6) (the circuit formed of the sample hold circuit SH2, the comparator OP2 and the like), and acquires substantially the same manner of operation and advantageous effects.
    [0076] [0076]
    [0077] [0077] In this manner, in the embodiment 4, as an output voltage VD4 of the comparator OP4, a voltage VDI substantially equal to the voltage VDI explained in the embodiment 1 or the embodiment 3 is outputted when the voltage of the X capacitor C100 {or the voltage VA or the like) is rising, and a voltage VD2 substantially equal to the voltage VD2 explained in the embodiment 2 or the embodiment 3 is outputted when the voltage of the X capacitor C100 (or the voltage VA or the like) is falling.
    [0079] [0079] [Embodiment 5] An embodiment 5 is an embodiment obtained by modifying the embodiment 1. The embodiment 5 differs from the embodiment 1 with respect to points such as the manner of generating a voltage VA and the like and the sophistication of a circuit and the like.
    [0080] [0080] Hereinafter, the embodiment 5 is described in detail.
    [0081] [0081] The control circuit 15 according to the embodiment 5 includes: a voltage dividing circuit having resistances R1 and R10; an operation amplifier OP51; a sample hold circuit SHS; a level shift circuit LS of a voltage; a comparator OPS; a counting unit CNT.
    [0082] [0082] First, the voltage dividing circuit having the resistances R1 and R10 is described. In the embodiment 1 (see Fig. 1), voltage division is performed by connecting the resistances R1, R2 and R3 in series between the cathodes of the diodes 1 and 2 and a GND, and a voltage at the connecting portion between the resistances R1 and R2 is set as a voltage VA (first voltage), and a voltage at the connecting portion between the resistances R2 and R3 is set as a voltage VC (second voltage). However, the embodiment 5 differs from the embodiment 1 with respect to a point that, as shown in Fig. 9, voltage division is performed by connecting the resistances R1 and R10 in series between the cathodes of the diodes 1 and 2 and the GND, and a voltage VAS is taken out from a connecting portion between the resistances R1 and R10.
    [0083] [0083] Next, the operation amplifier OP51 and the sample hold 089circuit SHS are described. The embodiment 5 differs from the embodiments 1 to 4 with respect to a point that the operation amplifier OPS! is provided between a voltage division part {the connecting part between the resistances R1 and R10) and the sample hold circuit (SHS).
    [0084] [0084] Next, the embodiment 5 differs from the embodiments 1 to 4 with respect to a point that the level shift circuit LS is provided to the control circuit 15.
    [0085] [0085] To describe the comparator OPS, an inverted input terminal (-) of the comparator OPS is connected to an output part of the sample hold circuit SHS (a side of the capacitor C5 opposite to the GND), and a voltage VBS outputted from the sample hold circuit SHS is inputted to the comparator OPS.
    [0086] [0086] Fig. 10 is a view for describing operation timing of the power source device 105 (and the control circuit 15 of the power source device 105) according to the embodiment 5.
    [0087] [0087] [Embodiment 6] An embodiment 6 is an embodiment obtained by modifying the embodiment 5.
    [00883] [00883] Fig. 11 is a view for describing the circuit configuration of a power source device 106 (and a control circuit 16 of the power source device 106) according to the embodiment 6.
    [0089] [0089] To describe the subtraction circuit 201, the subtraction circuit 201 is formed of an operation amplifier OP61, and resistances R31, R32, R33 and R34 (R31 to R34 having the same resistance value).
    [0090] [0090] Next, the comparator OP62 is described. The voltage VG (=VA5-VB5) outputted from IO the subtraction circuit 201 is inputted to the non-inverted input terminal (+) of the comparator OP62, and a fixed voltage (reference voltage) VK is inputted to an inverted input terminal (-).
    [0091] [0091] Fig. 12 is a view for describing operation timing of the power source device 106 {and the 29 control circuit 16 of the power source device 106) according to the embodiment 6. Fig. 13isa view for describing a portion (a portion indicated by a symbol L6) shown in Fig. 12 in an enlarged manner.
    [0092] [0092] To explain the timing chart of the voltage VG (=VA5-VB5), the voltage VG is a voltage obtained by subtracting the voltage VBS, which is obtained by sample-holding a voltage VAS’, from the voltage VAS, which is a voltage at the connecting portion between the resistances R1 and R10 by the subtraction circuit 201 and hence, a voltage waveform of the voltage VG becomes a sawtooth-shaped waveform as shown in Fig. 12 and Fig. 13.
    [0093] [0093] Although the present invention has been descried based on the above-mentioned embodiments heretofore, the present invention is not limited to the above-mentioned embodiments. The present invention can be carried out in various modes without departing from the gist of the present invention. For example, the following modifications are also conceivable.
    [0094] [0094] (1) In the above-mentioned embodiments 1 to 6, a MOSFET element is used as the switches (SD, SWI, SW2 and the like). However the other semiconductor such as an IGBT element can be used in place of the MOSFET element.
    [0095] [0095] Reference Signs List 11, 12, 13, 14, 15, 16: control circuit 101, 102, 103, 104, 105, 106: power source device AC: alternating current
    DC: direct current ACI, AC2: input terminals OUT: output OUTIL, OUT2: output terminals C21: capacitor (for smoothing) Ct, C2, C4, CS: capacttor (for sample-holding) C100: capacitor {X capacitor) COV: DC-DC convertor 51: AC-DC convertor REC: rectifier circuit D1, D2, D21, D22, D23, D24: diode Ri, R2, R3, R10: resistance (for dividing voltage) R20: resistance (for discharging) R21, R22, R23, R24, R31, R32, R33, R34: resistance SWI, SW2, SW4, SWS: switch (for sample-holding) SW41, SW42, SW43: switch (for switching circuit) SD: switch (for discharging) SH1, SH2, SH4, SHS: sample hold circuit OP1, OP2, OP4, OP5, OP62: comparator OP51, OP52, OP61: operation amplifier CNT: counting unit OR!: logical sum element LS: level shift circuit 201: subtraction circuit CP: clock pulse VA: voltage at connecting portion between resistances R1 and R2 VC: voltage at connecting portion between resistances R2 and R3 V10: differential voltage between connecting portion between resistances R1 and R10 and connecting portion between resistances R2 and R3 VAS: voltage at connecting portion between resistances R1 and R10 VAS”: voltage outputted from operation amplifier OP51 VB1: sample hold voltage at connecting portion between resistances R1 and R2 (voltage VA) VB2: sample hold voltage at connecting portion between resistances R2 and R3 (voltage VC) VBS: sample hold voltage of output voltage (voltage VAS") of operation amplifier OP51 VCS: voltage outputted from level shift circait LS VDI: voltage outputted from comparator OPI
    VD2: voltage outputted from comparator OP2 VD3: voltage outputted from logical sam element ORI VD4: voltage outputted from comparator OP4 VDS: voltage outputted from comparator OPS VDO: voltage outputted from comparator OP62 VE: voltage outputted from counting unit CNT (for discharge command) t11, 112, 113, £21, 22, (23: point of time T: cycle T11, T21: predetermined time until start of discharging IO TI10: sample hold cycle VJ, VK: reference voltage (fixed voltage)
    权利要求:
    Claims (12)
    [1]
    Conclusions i. Control circuit for controlling a discharge of a capacitor connected between power source lines with different polarities of an alternating current from an AC-DC converter which receives inputs of the alternating current, converts the alternating current to a direct current, and outputs the direct current, the control circuit detects a state of change of a voltage of the capacitor, and controls the discharge such that a charge stored in the capacitor is discharged based on the state of change.
    [2]
    The control circuit of claim 1, wherein the control circuit performs detection of the state of change of the voltage of the capacitor by setting a first voltage obtained by level shifting of the voltage of the capacitor and a first voltage. second voltage increased or decreased from the first voltage, and by performing a comparison operation between a voltage obtained by sample holding of the first or second voltage at any fixed time and the first or second voltage at which sample holding has not been applied.
    [3]
    The control circuit according to claim 2, wherein the comparison operation performed by the control circuit is a comparison operation which compares and detects a magnitude ratio of the voltage obtained by sample holding and the voltage to which sample holding is not applied. or a comparison operation that outputs a voltage difference.
    [4]
    Control circuit according to claim 2 or 3, wherein the control circuit performs detection of the state of change of the voltage of the capacitor by detecting, starting from voltage values of the first voltage, the second voltage, and a voltage obtained by sample holding of one of the the first or the second voltage as a first voltage characteristic line, a second voltage characteristic line and a sample-hold voltage characteristic line expressed respectively with a time course, of an intersection between the sample-hold voltage characteristic line and the voltage characteristic line of the voltage on which sample -holding has not been applied from the first and second stresses.
    [5]
    The control circuit according to claim 1, wherein the control circuit performs the detection of the state of change of the voltage of the capacitor by comparing an output obtained by performing a comparison operation between a voltage obtained by sample holding a first voltage. voltage obtained by level shift of the voltage of the capacitor and the first voltage to which sample holding is not applied with a reference voltage.
    [6]
    A control circuit according to any one of claims 1 to 5, wherein when a state is detected that there is no change in the change state for a fixed period, the control circuit controls the discharge such that a charge stored in the capacitor is discharged.
    [7]
    The control circuit according to claim 6, wherein the control circuit performs detection of a state where there is no change in the change state for a fixed period by counting a time of the state where there is no change in the change state.
    [8]
    A control circuit according to any one of claims 1 to 7, wherein the control circuit detects a change state of at least one of rise or fall of the voltage of the capacitor, and controls the discharge such that a charge stored in the capacitor is discharged based on of the state of change.
    [9]
    The control circuit of claim 8, wherein the control circuit detects the change state of rise of the voltage of the capacitor, and controls the discharge such that a charge stored in the capacitor is discharged based on the change state.
    [10]
    The control circuit of claim 2, the control circuit comprising: a first voltage generating unit that generates the first voltage obtained by level shifting the voltage of the capacitor connected between the power source lines of different polarities; a second voltage generating unit that generates a second voltage that is less than the first voltage; a sample hold unit for sample holding of the first or second voltage, the sample hold unit comprising: a sample hold capacitor for the first or second voltage; and a sample hold switch disposed between the first or second voltage generating unit and the sample hold capacitor; a comparison operation unit that detects the change state by performing a comparison operation between a sample hold voltage obtained by sample holding by the sample hold unit from the first and second voltages and the voltage to which sample holding is not applied from the first and second voltages; and a discharge unit which discharges a charge stored in the capacitor connected between the power source lines of different polarities based on the detected change state.
    [11]
    The control circuit of claim 5, the control circuit comprising: a first voltage generating unit that generates the first voltage obtained by level shifting the voltage of the capacitor connected between the power source lines of different polarities; a sample hold unit for the first voltage, the sample hold unit comprising: a sample hold capacitor for the first voltage; and a sample hold switch disposed between the first voltage generating unit and the sample hold capacitor; a comparison operation unit that detects the state of change by comparing an output calculated based on a sample hold voltage for the first voltage obtained by sample holding of the first voltage by the sample hold unit and the first voltage to which sample hold has not been applied by the sample hold unit with a reference voltage; and a discharge unit which discharges a charge stored in the capacitor connected between the power source lines of different polarities based on the detected change state.
    [12]
    A power source device, comprising: an AC-DC converter that receives inputs of an alternating current and outputs a direct current; a capacitor connected between power source lines with different polarities of the alternating current; and the control circuit of any one of claims 1 to 11 which controls a discharge of the capacitor.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20120112564A1|2010-04-22|2012-05-10|Chin-Ho Wu|Discharging module applied in a switched-mode power supply and method thereof|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP2019166878|2019-09-13|
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